Worked on floorplan for Block/SoC and should be able to plan Macro placement, Port Placement etc.
Should be aware of all the Sanity checks ¬¬and building the Quality metrices for Physical Design.
Should be well versed with placement optimization techniques and well aware with the complete flow of placement.
Deep understanding of the CTS concepts and should be able to do clock tree planning for Block/SoC for Multiclock designs.
Well verse with all the Routing challenges in the Design.
Should have good exposure to high frequency multi voltage design convergence.
Understanding of deep sub-micron design problems and solutions (Skew analysis, clock divergence, signal integrity, DFM etc.)
Should have good understanding of Base/Metal DRC problems in Physical verification.
Well versed with Tcl/Perl scripting.
Full exposure to all aspects of design flows like floor-planning, placement, CTS, routing, crosstalk avoidance, physical verification
Strong problem-solving skills and communication skills.
B.Tech/B.E./M.E/M.Tech Degree in Electrical/Electronics science engineering with at least 2+ years of VLSI industry experience in block level or chip level Timing closure & Physical Design activities.
STA Engineer / Sr. STA Engineer (2-6) years - Apply Now
Thorough knowledge and understanding of static timing analysis concepts.
Well aware on the STA flow and should be able to build the STA flow independently.
Should have a strong understanding of Constraints and able to modify and build the constraints with collaboration of RTL and DFT team.
Well versed with the Block level / SOC level timing closure (STA) methodologies, ECO generation and predictable convergence.
Should be able to understand the problems occur in in STA due to Physical design and able to provide right feedback to PD team.
Should have good exposure to high frequency multi voltage design convergence.
Full exposure to all aspects of STA including: Timing, DRCs, Sanity Checks, Annotation issues, Multivoltage STA flow enablement, Noise, Crosstalk etc.
Well versed with Tcl/Perl scripting.
Strong problem-solving skills and communication skills.
B.Tech/B.E./M.E/M.Tech Degree in Electrical/Electronics science engineering with at least 2+ years of VLSI industry experience in block level or chip level Timing closure & Physical Design activities.
Independent planning and execution of Synthesis Netlist-to-GDSII.
Should be able to Lead/Mentor a team.
Independent planning and closure of the Synthesis Netlist to Route opt netlist.
Worked on floorplan for Block/SoC and should be able to plan Macro placement, Port Placement etc.
Should be aware of all the Sanity checks ¬¬and building the Quality metrices for Physical Design.
Understanding and able to architect the Power planning for the Block/SoC.
Should be well versed with placement optimization techniques and well aware with the complete flow of placement.
Deep understanding of the CTS concepts and should be able to do clock tree planning for Block/SoC for Multiclock designs.
Well verse with all the Routing challenges in the Design and Pre-Measures need to be taken to converge the design. Should be able to understand the congestion issues and able to make the guidelines for team.
Should have good exposure to high frequency multi voltage design convergence.
Understanding of deep sub-micron design problems and solutions (Skew analysis, clock divergence, signal integrity, DFM etc.)
Should have good understanding of Base/Metal DRC problems in Physical verification.
Well versed with Tcl/Perl scripting.
Full exposure to all aspects of design flows like floor-planning, placement, CTS, routing, crosstalk avoidance, physical verification
Strong problem-solving skills and communication skills.
B.Tech/B.E./M.E/M.Tech Degree in Electrical/Electronics science engineering with at least 6+ years of VLSI industry experience in block level or chip level Timing closure & Physical Design activities.
Independent planning and execution of Route Netlist-to-STA Signoff.
Thorough knowledge and understanding of static timing analysis concepts.
Should be able to Lead/Mentor a team.
Well aware on the STA flow and should be able to build the STA flow independently.
Should have a strong understanding of Constraints and able to modify and build the constraints with collaboration of RTL and DFT team.
Well versed with the Block level / SOC level timing closure (STA) methodologies, ECO generation and predictable convergence.
Should be able to understand the problems occur in in STA due to Physical design and able to provide right feedback to PD team.
Well aware of the Timing ECO flow with industry standard tools and able to setup the complete flow and mentoring the team.
Should have good exposure to high frequency multi voltage design convergence.
Good understanding of clock networks.
Understanding of deep sub-micron design problems and solutions (Skew analysis, clock divergence, signal integrity, DFM etc.)
Full exposure to all aspects of STA including: Timing, DRCs, Sanity Checks, Annotation issues, Multivoltage STA flow enablement, Noise, Crosstalk etc.
Well versed with Tcl/Perl scripting.
Strong problem-solving skills and communication skills.
B.Tech/B.E./M.E/M.Tech Degree in Electrical/Electronics science engineering with at least 6+ years of VLSI industry experience in block level or chip level Timing closure & Physical Design activities.
Aware of Compression architecture, various mode of Scan
Hands-on Scan insertion and ATPG .
Coverage analysis and debug.
Pattern simulations with timing and No-timing.
MBIST hands-on using mentor tools.
Experience in Synopsys/mentor graphics tools are preferable.
B.Tech/B.E./M.E/M.Tech Degree in Electrical/Electronics science engineering with at least Trained/1+ years of VLSI industry experience in block level or chip level DFT/ATPG/Mbist activities.
Looking for a DFT lead position with strong hands-on experience in DFT architecture design at RTL, Scan Synthesis and ATPG along with Post-silicon debug.
Should have extensive understanding of the ATPG compression logic, JTAG.
Understanding of MBIST and hands-on is value addition.
Driving the DFT micro level architecture at RTL and come up with best methodology strategies which help on Area, Timing, Power
Hands-on with scan insertion, DRC analysis, STA test mode Constraints development.
Making Sure Equivalence checking with post-scan insertion.
ATPG coverage analysis and improvements. Pattern simulations pre/post-timing.
Co-working with SOC team on pattern porting and part of the post-silicon debug.
Working on the advanced fault models and DFT methodology bring-up for new technology nodes.
Mentoring and guiding the Juniors in the team.
B.Tech/B.E./M.E/M.Tech Degree in Electrical/Electronics science engineering with at least 8+ years of VLSI industry experience in block level or chip level DFT activities.
