SERVICES

DFT (Design For Testability) Provide expertise in Design for Test including DFT Architecture , Pattern Generation and optimization, Simulation with timing and no-timing, RTL and Gate level Debugging, Coverage enhancements, MBIST, JTAG boundary Scan.
  • IP & SoC Level DFT
  • Scan Insertion and Fault Coverage analysis
  • Scan Constraints development along with STA team
  • ATPG DRC & Pattern verification in Compression/Bypass mode
  • Coverage analysis and improvement
  • MBIST insertion and verification
  • Power reduction techniques for Scan Shift/Capture
  • JTAG Boundary Scan
  • DFT for special IPs like Serdes, USB, ADC, DAC, Class-D amp, Band Gap, Voltage Regulator, LDO
Tools: Tessent MBIST, DFTAdvisor, FastScan, TestKompress, DFTCompiler, TetraMax, VCS, NCSim, ModelSim, Xilinx ISE.
Synthesis Strong Synthesis skills provide high level of optimizations strategies and early feedback to the design team to close on the RTL. Successful tapeouts on technology nodes 45nm to 5nm for complex SoCs
  • Design Synthesis and RTL feedback to improve design.
  • Constraints Coding
  • Logical and Physical Synthesis
  • 2 or 3 pass optimizations.
  • Multi Voltage/Power optimizations , Low Power optimizations.
  • IP and SoC Synthesis
  • Low Power Checks (UPF) using VCLP
Tools: DC/DC-Topo (Synopsys) , Genus (Cadence)
STA(Static Timing Analysis) Expert in SoC and IP Static timing analysis, Constraint coding, Flow development from scratch, Generation of timing ECOs and converging the entire SoC design with exhaustive checklist. Successful tapeouts on technology nodes 45nm to 5nm for complex SoCs
  • Constraints Development
  • Flow Development from Scratch
  • Exhaustive Prelayout Checks.
  • Spef verification / Starrc Quality assessment
  • Timing Analysis and Feedback to Design/Constraints/PD team
  • Cross Talk and Noise analysis
  • Power ECO (Buffer Removal / Cell Downsize)
  • Timing ECOs
  • IP and SoC level timing closure
Tools: Primetime (Synopsys) , Tempus (Cadence)
Design Verification Team has capabilities to perform IP and SoC level Design Verification using latest methdologies (UVM/SV-UVM). Succesfully delivered projects (Ips, Compelte SoCs).
  • IP and SoC level verification
  • Verification Environment including Assertions.
  • Automated Checkers and Constraint Random Verification
  • Standard Protocals: Ethernet , ATM , Digital Secure I/O, SD Memory, AXI, AHB , APB.
  • Methodologies: SV , UVM , C/C++, System C , OVM
Tools: VCS , Incisive , Questa , FPV , Jasper Gold , Palladium-2, Spyglass , LINT
Physical Design & Physical Verification Team have a capability to take the Synthesized netlist from Floorplan to Routeopt Exit with exhaustive quality checks at each and every stage including exhaustive DRC/LVS/ERC checks for IP and SoC on lower technology nodes (45nm to 5nm). Boundary and interface DRC/LVS checks closure with right set of guidelines provided to implementation team.
  • Floorplanning
  • Placement and MMMC optimizations.
  • Clock Tree Synthesis (MCTS , HCTS, Regular CTS)
  • Exhaustive Quality checks on every stage
  • RouteOpt Exit with Correlation with STA and DRC checks from PV
  • Physical Verification using Caliber and ICV
  • Low Power Checks (UPF) using VCLP
Tools: ICC/ICC2 (Synopsys) , Innovus (Cadence)
Embedded, FPGA & IoT We facilitate our clients with the complete end-to-end Embedded Product Development Services, End to End FPGA design services for IP development and development of IoT with modification of existing solutions in the area of industrial and home automation and security.
  • Product Innovation, Technical Feasibility
  • Prototyping and Development
  • BareMetal C programming
  • FREE ROTS
  • Connected IoT device
  • Amazon EC2 servers
  • Mechanical 3D print prototyping
  • Electronics PCB assembly

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